In a semiconductor device, for example, a multilayer wiring made of a metal film containing Cu (copper) or Al (aluminum) as a main component is formed on a semiconductor substrate on which a semiconductor element such as a CMIS (Complementary Metal Insulator Semiconductor) transistor is formed, and a final passivation film is formed on the multilayer wiring.
Japanese Patent Application Laid-Open Publication No. 2003-234348 (Patent Document 1) discloses a technique in which a redistribution line containing Cu as a main component is formed on a final passivation film and an electrode pad formed in an uppermost layer wiring below the passivation film is electrically connected to the redistribution line.
FIG. 25 of Japanese Patent Application Laid-Open Publication No. 2012-4210 (Patent Document 2) discloses a structure in which a wire 20 is connected to a pad 18 formed so as to partially cover an upper surface and a side surface of a redistribution line 15 containing Cu as a main component.
The abstract of Japanese Patent Application Laid-Open Publication No. 2000-306938 (Patent Document 3) discloses that a redistribution layer 6 made of aluminum alloy formed on a passivation film 4 is completely covered with a barrier metal film 8 having a projecting part 9 that projects on the passivation film 4, thereby suppressing the occurrence of migration and corrosion of the redistribution layer 6.
“Development of highly reliable Cu wiring of L/S=1/1 for chip to chip interconnection” (Non-Patent Document 1) discloses a structure in which a metal barrier film formed by electroless plating is provided on an upper surface and a side surface of a Cu wiring formed by SAP (Semi-Additive Process) in order to improve the reliability of the Cu wiring.